1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a latch.
2. Description of the Prior Art
FIG. 9 shows a schematic diagram of a configuration of a general shift register in a prior art embodiment. A shift register consists of plural latches 1000 connected in series. A unit latch 1000 consists of a pair of half-latches 100. A control signal generator 60 generates control signals T and TC based upon a clock signal CLK. The control signals T and TC have a negative logic relation with each other, and they are also supplied to every one of half-latches 100 connected in series. Each of half-latches 100 has control signal input ends I1, I2.
In general, the control signal generator 60 receives the clock signal CLK, and inverters 61 and 62 together produce the control signal T having a positive logic relation with the clock signal while the inverter 61 alone produces the control signal TC having a negative logic relation with the clock signal. A delay time caused by the inverter 62 is inserted between those control signals.
FIG. 10 shows an internal configuration of one of the half-latches 100. An input line 1 leads an input signal D applied to the half-latch 100 into a transmission gate 21. The transmission gate 21 is connected through a signal line 2 to an inverter 23, which inverts the input signal D to apply an output signal Q to an output line 3.
The output line 3 is connected to an inverter 24, which inverts the output signal Q and produce an output signal QC to apply it through a transmission gate 22 to the inverter 23.
The transmission gate 21 consists of an N channel transistor 21a and a P channel transistor 21b; the control signal input end I1 is connected to a gate of the transistor 21a while the control signal input end I2 is connected to a gate of the transistor 21b. Similarly, the transmission gate 22 consists of an N channel transistor 22a and a P channel transistor 22b; the control signal input end I2 is connected to a gate of the transistor 22a while the control signal input end I1 is connected to a gate of the transistor 22b.
The transmission gate 21 and the inverter 23 cooperate with each other to receive the input signal D and output the output signal Q, both of which function as a main unit en bloc. The transmission gate 22 and the inverter 24 cooperate with each other to retain the output signal Q, both of which function as a feedback unit en bloc.
FIG. 11 shows a timing chart for illustrating a circuit operation of the half-latch 100 shown at left side in FIG. 9. Receiving the clock signal CLK, the inverter 61 delays it by a period (t.sub.12 - t.sub.11) to produce the control signal TC having a negative logic relation with the clock signal CLK, and the inverter 62 further delays the control signal TC by a period (t.sub.13 - t.sub.12) to produce the control signal T having a positive logic relation with the clock signal CLK. A delay time (t.sub.13 - t.sub.11) is inserted between the clock signal CLK and the eventual control signal T.
Operations of the transmission gates 21 and 22 based upon the control signals T and TC will be described in conjunction with operating periods of the transistors 21a, 21b, 22a and 22b. Part hatched in FIG. 11 represents that each transistor turns on.
The operation of the half-latch 100 shown in FIG. 10 can be divided into a data input (update) operation by the main unit and a data retaining operation by the feedback unit. For example, turning the transmission gate 21 on in the main unit causes the input signal D to be taken in, and turning the transmission gate 22 on in the feedback unit causes the output signal Q to be retained.
When the control signal T is in the High state and the control signal TC is in the Low state (for a period t.sub.13 through t15), the transmission gate 21 turns on while the transmission gate 22 turns off. Thus, the input signal D input to the input line 1 is applied to the inverter 23 via the signal line 2, and the output signal Q obtained by practicing a logic inversion of the input signal D is applied to the output line 3.
On the other hand, when the control signal T is in the Low state and the control signal TC is in the High state (for a period t.sub.16 through t.sub.12), the transmission gate 22 turns on while the transmission gate 21 turns off. Thus, the inverters 23 and 24 together make a loop, and thus, the output signal Q is retained in safety in the output line 3 while the signal QC obtained by logically inverting the output signal Q is retained in safety in the signal line 2.
In this way, the data input (update) operation by the main unit and the data retaining operation by the feedback unit are repetitively practiced in the half-latch 100, and thereby the shift register shown in FIG. 9 updates its value successively.
However, each of the transmission gates 21 and 22 consists of a complementary conductive transistor pair connected in parallel, and since the control signals T and TC which control these transistors to turn them on or off vary with a delay time of (t.sub.13 - t.sub.12) or (t.sub.16 - t.sub.15) inserted between them, both of the transmission gates 21 and 22 turn on for such periods of time. This is proved in FIG. 11 where there are several overlappings of the hatched part for the same time periods.
Time t.sub.15 through time t.sub.16, the transistor 22a begins turning on while the transistor 21a stays in the ON-state. Thus, both the transmission gates 21 and 22 turn on for this time period, and accordingly, the input signal D and the signal QC are transmitted to the signal line 2. As shown in FIG. 9, however, the identical control signals T and TC are applied to each of the half-latches 100 connected in series, and hence, when one., of those half-latches 100 starts the data retaining operation in the feedback unit, that half-latch never receives a new signal (i.e., the output signal Q of the preceding one to that half-latch, or the input signal D to that half-latch) from the preceding half-latch. A logic inversion of the input signal D by the inverter 23 is already completed at a point of time t.sub.15.
Thus, time t.sub.15 through time t.sub.16, even if both the transmission gates 21 and 22 open, the input signal D is safely applied to the input line 1, the signal QC having a positive logic relation with the input signal D is safely applied to the signal line 2, and the output signal Q having a negative logic relation with the input signal D is safely applied to the output line 3, respectively.
At time t.sub.16, both the transistors 21a and 21b of which the transmission gate 21 is comprised turn off, and both the transistors 22a and 22b of which the transmission gate 22 is comprised turn on; and accordingly, the loop made up with the inverters 23 and 24 brings the half-latch 100 into a data retaining state.
At time t.sub.12, however, the transistor 21b turns on to turn the transmission gate 21 on, and accordingly, the half-latch 100 is in a state of transition from the data retaining operation to the data input operation. However, since the transistor 22b has been still in the ON-state since time t.sub.12 or earlier, the transmission gate 22 turns on until time t.sub.13.
In this case, since the preceding one to that half-latch 100 also updates data, the output signal D newly input to the signal line 1 and the signal QC retained in the signal line 2 collide with each other time t.sub.12 through time t.sub.13 if those signals are different in logic from each other. Collision of such signals having different logic values causes a large through-current, which leads to the problem that a demand should be increased. Additionally, a demand of the inverter 23 to which a potential at the signal line 2 is input is also increased because slow rising and slow falling of signals are caused in the signal line 2 where signals collide with each other.
In such an ordinary latch operation based upon positive and negative clocks, signals collided with each other if data retained in inputting data and data newly input are different in logic from each other, because a delay time inserted between positive and negative clocks causes transistors in a main unit and a feedback unit to be simultaneously turning on. In the above-mentioned latch, the inverter 24 in the feedback unit, which is an auxiliary part for retaining data, makes through-current flow during a variation in a signal each time data in the latch varies, and consequently, an extra electric power is consumed.